JPH0151093B2 - - Google Patents

Info

Publication number
JPH0151093B2
JPH0151093B2 JP53062670A JP6267078A JPH0151093B2 JP H0151093 B2 JPH0151093 B2 JP H0151093B2 JP 53062670 A JP53062670 A JP 53062670A JP 6267078 A JP6267078 A JP 6267078A JP H0151093 B2 JPH0151093 B2 JP H0151093B2
Authority
JP
Japan
Prior art keywords
node
level
potential
circuit
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53062670A
Other languages
English (en)
Japanese (ja)
Other versions
JPS54153565A (en
Inventor
Akira Osami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP6267078A priority Critical patent/JPS54153565A/ja
Priority to US06/041,433 priority patent/US4330719A/en
Priority to DE2920966A priority patent/DE2920966C2/de
Publication of JPS54153565A publication Critical patent/JPS54153565A/ja
Publication of JPH0151093B2 publication Critical patent/JPH0151093B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
JP6267078A 1978-05-24 1978-05-24 Semiconductor circuit using insulation gate type field effect transistor Granted JPS54153565A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP6267078A JPS54153565A (en) 1978-05-24 1978-05-24 Semiconductor circuit using insulation gate type field effect transistor
US06/041,433 US4330719A (en) 1978-05-24 1979-05-22 Circuit using insulated-gate field-effect transistors
DE2920966A DE2920966C2 (de) 1978-05-24 1979-05-23 Schaltkreis zum Auffrischen des Gatespannungspegels eines Isolierschicht-Feldeffekttransistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6267078A JPS54153565A (en) 1978-05-24 1978-05-24 Semiconductor circuit using insulation gate type field effect transistor

Publications (2)

Publication Number Publication Date
JPS54153565A JPS54153565A (en) 1979-12-03
JPH0151093B2 true JPH0151093B2 (en]) 1989-11-01

Family

ID=13206951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6267078A Granted JPS54153565A (en) 1978-05-24 1978-05-24 Semiconductor circuit using insulation gate type field effect transistor

Country Status (3)

Country Link
US (1) US4330719A (en])
JP (1) JPS54153565A (en])
DE (1) DE2920966C2 (en])

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5625290A (en) * 1979-08-07 1981-03-11 Nec Corp Semiconductor circuit
JPS5915211B2 (ja) * 1979-11-27 1984-04-07 富士通株式会社 発振回路
JPS5693422A (en) * 1979-12-05 1981-07-29 Fujitsu Ltd Level-up circuit
JPS5683131A (en) * 1979-12-11 1981-07-07 Nec Corp Semiconductor circuit
JPS56122526A (en) * 1980-03-03 1981-09-26 Fujitsu Ltd Semiconductor integrated circuit
JPS56129570A (en) * 1980-03-14 1981-10-09 Mitsubishi Electric Corp Booster circuit
DE3105147A1 (de) * 1981-02-12 1982-09-09 Siemens AG, 1000 Berlin und 8000 München Integrierte digitale halbleiterschaltung
JPS589432A (ja) * 1981-07-08 1983-01-19 Toshiba Corp 論理回路
JPS58185091A (ja) * 1982-04-24 1983-10-28 Toshiba Corp 昇圧電圧出力回路および昇圧電圧出力回路を備えたアドレスデコ−ド回路
US4622479A (en) * 1982-12-14 1986-11-11 Thomson Components-Mostek Corporation Bootstrapped driver circuit for high speed applications
DE3371961D1 (en) * 1983-05-27 1987-07-09 Itt Ind Gmbh Deutsche Mos push-pull bootstrap driver
US4678941A (en) * 1985-04-25 1987-07-07 International Business Machines Corporation Boost word-line clock and decoder-driver circuits in semiconductor memories
US4736121A (en) * 1985-09-10 1988-04-05 Sos Microelettronica S.p.A. Charge pump circuit for driving N-channel MOS transistors
KR920010749B1 (ko) * 1989-06-10 1992-12-14 삼성전자 주식회사 반도체 집적소자의 내부전압 변환회로
US20050083095A1 (en) * 2003-10-16 2005-04-21 Tsvika Kurts Adaptive input/output buffer and methods thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3663835A (en) * 1970-01-28 1972-05-16 Ibm Field effect transistor circuit
US3743862A (en) * 1971-08-19 1973-07-03 Texas Instruments Inc Capacitively coupled load control
US3806741A (en) * 1972-05-17 1974-04-23 Standard Microsyst Smc Self-biasing technique for mos substrate voltage
US3806738A (en) * 1972-12-29 1974-04-23 Ibm Field effect transistor push-pull driver
US3808468A (en) * 1972-12-29 1974-04-30 Ibm Bootstrap fet driven with on-chip power supply
JPS50105264A (en]) * 1974-01-25 1975-08-19
JPS51132068A (en) * 1975-05-13 1976-11-16 Nippon Telegr & Teleph Corp <Ntt> Inversional amplification circuit

Also Published As

Publication number Publication date
DE2920966C2 (de) 1984-02-02
DE2920966A1 (de) 1979-11-29
JPS54153565A (en) 1979-12-03
US4330719A (en) 1982-05-18

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